citac1ch Project Status (05/23/2011 - 02:12:11)
Project File:	citac1ch.ise	Implementation State:	Programming File Generated
Module Name:	citac	Errors:	No Errors
Target Device:	xc3s50an-4tqg144	Warnings:	26 Warnings
Product Version:	ISE 11.1	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Setup: 0, Hold: 0) (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	405	1,408	28%
Number used as Flip Flops	383
Number used as Latches	22
Number of 4 input LUTs	459	1,408	32%
Number of occupied Slices	358	704	50%
Number of Slices containing only related logic	358	358	100%
Number of Slices containing unrelated logic	0	358	0%
Total Number of 4 input LUTs	553	1,408	39%
Number used as logic	459
Number used as a route-thru	94
Number of bonded IOBs	8	108	7%
Number of BUFGMUXs	4	24	16%
Number of DCMs	1	2	50%
Average Fanout of Non-Clock Nets	3.50

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	po 23. 5 02:12:26 2011	0	23 Warnings	4 Infos
Translation Report	Current	po 23. 5 02:12:36 2011	0	0	0
Map Report	Current	po 23. 5 02:12:44 2011	0	0	3 Infos
Place and Route Report	Current	po 23. 5 02:13:04 2011	0	3 Warnings	3 Infos
Power Report
Post-PAR Static Timing Report	Current	po 23. 5 02:13:10 2011	0	0	3 Infos
Bitgen Report	Current	po 23. 5 02:13:20 2011	0	0	1 Info

 

Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	čt 19. 5 00:54:14 2011
Post-Place and Route Simulation Model Report	Out of Date	út 17. 5 19:04:46 2011

Date Generated: 05/26/2011 - 22:37:09